The present invention relates to a flash memory device and, more particularly, to a NAND-type flash memory device with a multi-page program operation, a multi-block erase operation, and a multi-page read operation.
A NAND-type flash memory device such as a non-volatile memory device includes memory cells (or memory cell transistors). Each of the memory cell transistors includes a floating gate transistor having a source, drain, a floating gate, and a control gate. The memory cell transistor stores data therein by varying the amount of charges of the floating gate to store data therein. For example, a memory cell transistor is programmed by injecting electrons into a floating gate so that a threshold voltage becomes higher than a predetermined voltage. On the other hand, the memory cell transistor is erased by drawing electrons from the floating gate so that a threshold voltage becomes lower than a predetermined voltage. In a NAND-type flash memory device, a memory cell transistor is erased/programmed according to the Flower-Nordheim tunneling (F-N tunneling) effect, which is explained in U.S. Pat. No. 5,671,176 entitled xe2x80x9cSemiconductor Memory Device Including Program Inhibit Capacitors And Method For Controlling Program-disturb Of Non-selected Memory Cellsxe2x80x9d.
As illustrated in FIG. 1, a conventional NAND-type flash memory device includes a block address register 20, a predecoder 30, and a mat selecting circuit 40. The block address register 20 latches a block address BA in response to a control signal LOAD_BLK. The predecoder 30 decodes an output of the block address register 20 to output decoding signals Pj, Qj, and Rj. The mat selecting circuit 40 activates one of mat selecting signals MSEL1xcx9cMSEL4 in response to a mat address MA that is inputted from an external source.
Also the NAND-type flash memory device includes a memory cell array for storing information. The memory cell array is divided into a plurality of mats MATi (i=1xcx9c4) each having a plurality of rows or wordlines, a plurality of columns or bitlines, and a plurality of memory cells arranged in a matrix of the rows and the columns. The memory cells at the respective columns constitute a NAND string, and the memory cells at the respective rows constitute a page. Although not shown in the figure, the NAND string includes memory cells that are serially coupled between a string selection transistor and a ground selection transistor, as disclosed in the above-referenced U.S. Pat. No. 5,671,176.
To simplify the explanation, peripheral components associated with one mat (e.g., MAT 1) will now be explained hereinbelow. The other mats MAT2-MAT4 have the same construction as the mat MAT1 and will not be explained in further detail.
A NAND-type flash memory device includes a row selection circuit having a plurality of row selectors X-DEC1xcx9cX-DECn each corresponding to their memory blocks BLK1-BLKn of each mat. Each of the selectors X-DEC1xcx9cX-DECn transfers wordline voltages to rows or wordlines of a corresponding memory block in response to a mat selection signal MSELi and decoding signals Pj, Qj, an Rj from a predecoder. For example, the row selector X-DEC1 transfers wordline voltages to rows or wordlines of a corresponding memory block in response to a mat selection signal MSEL1 and the decoding signals Pj, Qj, and Rj. Although not shown in the figure, the wordlines voltages are supplied from a high voltage generation circuit.
A page buffer circuit 50_1 is coupled to columns or bitlines (not shown) extended through the corresponding mat MAT1, and includes page buffers each corresponding to their columns. Each of the page buffers acts as a sense amplifier, a latch circuit, and a write driver. For example, a page buffer senses data from memory cells of a selection page through bitlines in a read operation, and temporarily latches the sensed data. The page buffer temporarily latches data to be programmed to a selection page in a program operation, and transfers the latched data to bitlines. An exemplary page buffer is disclosed in U.S. Pat. No. 5,712,818 entitled xe2x80x9cData Loading Circuit For Parallel Program Of Nonvolatile Semiconductor Memoryxe2x80x9d. A column pass gate circuit 60_1 partially selects columns of a corresponding mat, and couples page buffers of the selected columns to a data bus (not shown).
The NAND-type flash memory device shown in FIG. 1 iteratively carries out the same program operation in order to store page data in each mat. As shown in FIG. 2, after inputting a command 80h indicating the sequential data input (S10), an initial address is inputted (S12). Byte/word page data to be programmed to a mat (e.g., MAT1) selected according to an inputted address is sequentially loaded in page buffer circuit 50_1 through a column pass gate circuit 60_1 (S14). As a command 10h indicating the program execution is inputted (S16), the data loaded in the page buffer circuit 50_1 is to be programmed to the selected mat MAT1 (S18). The procedure (S10xcx9cS18) must be reiterated for programming each mat.
Similar to the program operation, read and erase operations must be reiterated for each mat unit. This leads to an undesirable decrease in an operation speed. Thus, what is needed is a new scheme to program/erase pages/memory blocks of mats at the same time.
In order to meet the above-mentioned necessity, the present invention provides a NAND-type flash memory device which carries out a multi-page program operation, a multi-page read operation, and a multi-block erase operation.
According to one aspect of the present invention, a NAND-type flash memory device comprise a plurality of mats, a plurality of row selectors, a plurality of page buffer circuits, a plurality of row selectors, a plurality of pass/fail check circuits, a plurality of reset signal generators, and a latch signal generator. Each of the mats includes a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns. Each of the row selectors corresponds to the memory blocks of the respective mats, and selects a corresponding memory block in response to block selection information. Each of the page buffer circuits corresponds to the mats, and senses data from a selected memory block of a corresponding mat through columns of a selected memory block and transfers data to be programmed to the columns of the selected memory block. Each of the column selectors corresponds to the mats, and partially selects the columns of the selected memory block. Each of the pass/fail check circuits corresponds to the mats, and determines whether data transferred from a corresponding buffer circuit through a column selector is pass data. Each of the reset signal generators corresponds to the mats, and generates a first reset signal of a corresponding mat when the transferred data is the pass data. The latch signal generator selects one of the mats in response to mat selection information.
Each of the row selectors includes a decoding circuit which generates a block selection signal in response to the block selection information, a register which stores an output of the decoding circuit when a latch signal of a corresponding mat is activated, a first switch which is coupled to a block wordline and transfers a high voltage to the block wordline when a value latched by the register indicates that a corresponding memory block is selected, a second switch which transfers wordline voltages to rows of a corresponding memory block in response to the high voltage on the block wordline, and a reset circuit which resets the register when the first signal is activated.
The NAND-type flash memory device further comprises a control logic for determining whether an externally applied command is a command indicating the input of sequential data and generating a second reset signal when the externally applied command is the command indicating the input of the sequential data. Each of the reset signal generators generates the first reset signal when the second rest signal is activated or when data from a corresponding page buffer circuit is pass data. The latch signal generator includes a pulse generator, for generating a pulse signal in response to a flag signal indicating an operating status of the memory device, and a plurality of decoders each corresponding to the mats and each generating a latch signal of a corresponding mat in response to the mat selection information when the pulse signal is generated. Each of the reset signal generators includes a pulse generator.